The present invention relates generally to fabrication of semiconductor devices, and more specifically to methods of fabricating double-gate semiconductor-on-insulator (SOI) transistors.
Double-gate transistors are not commonly used due to the significant challenges required in the manufacturing process despite the fact that they offer greater performance compared to conventional planar transistors.
U.S. Pat. No. 6,451,656 B1 to Yu et al. describes a double-gate transistor on semiconductor-on-insulator (SOI).
U.S. Pat. No. 6,413,802 B1 to Hu et al. describes a double-gate FinFFET on semiconductor-on-insulator (SOI).
U.S. Pat. No. 6,365,465 B1 to Chan et al. also describes a process for a double gate MOSFET on semiconductor-on-insulator (SOI).
U.S. Pat. No. 6,396,108 B1 to Krivokapic et al. describes a process for a double gate MOSFET on semiconductor-on-insulator (SOI).
Accordingly, it is an object of the present invention to provide improved methods of forming double gates silicon-on-insulator (SOI) transistors.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a substrate having an SOI structure formed thereover is provided. The SOI structure including a lower SOI silicon oxide layer and an upper SOI silicon layer. The SOI silicon layer is patterned to form a patterned silicon layer. A dummy layer is formed over the SOI silicon oxide layer and the patterned SOI silicon layer. The dummy layer is patterned to form a damascene opening therein exposing: a portion of the lower SOI silicon oxide layer; and a central portion of the patterned SOI silicon layer to define a source structure and a drain structure. Patterning the exposed lower SOI silicon oxide layer to form a recess. Gate oxide layer portions are formed around the exposed portion of the patterned SOI silicon layer. A planarized layer portion is formed within the final damascene opening. The planarized layer portion including a bottom gate and a top gate. The patterned dummy layer is removed to form the double gated SOI channel transistor.